Day 10: Infineon’s Embedded Systems Summer Course (2024)

Komma Vineetha giving todays presenation on ADC

08/06/24: Komma Vineetha is a seasoned Sr. Staff Engineer at Infineon Technologies, specializing in hardware design with extensive experience in ASIC, FPGA, and SoC development. With over 8 years in the industry, she has a robust background spanning roles at Bharat Electronics Limited and academic achievements from Gokaraju Rangaraju Institute of Engineering and Technology.

Vineetha K covers essential aspects such as the definition of signals, distinguishing between periodic and aperiodic signals, and their representation over time. She also discussed the process of converting analog signals to digital using sample and hold circuits and successive approximation ADCs. she also covered details the function of the sample and hold circuit in capturing and holding voltage for ADC conversion.

1. Filtering: This means removing unwanted parts of the signal.

• FIR and IIR: These are types of filters. They help clean up the signal by removing noise or unwanted frequencies.
• Convolution: This is a method used in filtering to combine two sets of information. It helps in smoothing or sharpening the signal.

2. Spectral Analysis: This involves looking at the signal in terms of its different frequencies, like how we can split light into a rainbow.

• Windowing: This technique helps in analyzing small sections of the signal to understand its frequency content better.
• DFT (Discrete Fourier Transform): This is a mathematical method used to transform the signal from the time domain (how it changes over time) to the frequency domain (what frequencies it contains). It helps in identifying the different components of the signal.

• Sample: This is the process of measuring the voltage of an input signal at a specific point in time. It’s like taking a snapshot of the signal.
• Hold: Once the signal is sampled, the circuit holds this voltage for a brief period using a capacitor. This held voltage is used for further processing.

Inside SAR ADC (Successive Approximation Register Analog-to-Digital Converter):

• RSRC, RSW2, and RSW1: These are resistors in the circuit.
• SWAQ: This is a switch that controls the acquisition process.
• CSHOLD: This is a capacitor that holds the sampled voltage.
• ADC Core: The core part of the ADC that includes SAR Logic and DAC (Digital-to-Analog Converter).
• SAR Logic: This part converts the held analog signal into a digital value.
• DAC: This is used within the SAR process to compare the held voltage with generated reference voltages.

What is Acquisition Time?

The acquisition time is the duration needed for the sample and hold circuit to settle and accurately sample the input signal.

A sample and hold circuit takes a quick snapshot of an input signal’s voltage and holds it steady using a capacitor, allowing an analog-to-digital converter (ADC) to accurately convert this steady voltage into a digital value. This process ensures that the signal is stable and not fluctuating during the conversion, leading to more accurate digital readings.

• Sampling the Voltage: The input voltage (VIN)is captured and held steady by a sample and hold (S/H) circuit.
• Starting the Conversion: The SAR starts with an initial guess and refines it. The DAC (Digital-to-Analog Converter) generates a voltage based on the SAR’s guess.
• Comparison: A comparator checks if the DAC’s output matches VIN​. If it doesn’t, the SAR updates its guess.
• Iteration: This process repeats, with the SAR adjusting its guess bit by bit, until the DAC’s output matches VIN.
• Result: When the DAC output equals VIN​, the SAR holds the final digital value, representing the analog input voltage.

Imagine you have a magic box that helps you turn light signals into numbers. This magic box has a few important parts: a special switchboard (SARMUX) that picks which light signal to look at, a clever number-making part (SAR ADC) that turns the light into a number, a helper (SARREF) that gives the right power for making the number, and a boss (SARSEQ) that tells the switchboard to pick the next signal. All these parts work together to quickly turn lots of light signals into numbers every second.

What does the “n” in “n-bit ADC” indicate?

The “n” in “n-bit ADC” indicates the resolution of the ADC, which is the number of bits in the digital value of the conversion.

How is the accuracy of an ADC defined?

Accuracy of an ADC is defined by how well the quantization levels match the analog input signal.

A quantization level is a specific value that an ADC can assign to a part of an analog signal when converting it into a digital signal.

Accuracy of an ADC is how closely the digital output values match the original analog signal.

What is the sampling rate of an ADC and how is it measured?

The sampling rate of an ADC is 1 Msps (Mega samples per second). It measures the number of samples taken per second.

Explain the precision of an ADC.

The precision of an ADC is the smallest voltage that the Least Significant Bit (LSB) of the digital output can represent.

List some common errors associated with ADCs.

Common errors associated with ADCs include Quantization Error, Offset Error, Integral Non-Linearity (INL), Differential Non-Linearity (DNL), Gain Error, and Aliasing.

1. Quantization Error:

• When converting an analog signal to digital, small differences between the actual signal and the digital value can occur because the ADC can only represent discrete levels.

2. Offset Error:

• This happens when the ADC’s output does not start at zero when the input is zero, causing all measurements to be slightly off.

3. Integral Non-Linearity (INL):

• INL is when the actual output of the ADC deviates from a straight line, meaning the digital output is not perfectly proportional to the analog input over the entire range.

4. Differential Non-Linearity (DNL):

• DNL occurs when the step sizes between successive digital values are not uniform, leading to some steps being too large or too small.

5. Gain Error:

• Gain error happens when the slope of the ADC’s output is not exactly what it should be, making the output too high or too low across the entire range.

6. Aliasing:

• Aliasing is when high-frequency signals are incorrectly interpreted as lower-frequency signals because the sampling rate is too low, causing distortion in the digital output.(oversampling is done to avoid aliasing).

formula for conversion

(2/3.3)*(2¹² -1)=2481.8181~2482/2481.

So, the digital output for an analog input of 2V with a 3.3V reference on a 12-bit ADC is approximately 2481/2482.

Total acquisition and conversion time=acquisition time+resolution (bits)+2

Total acquisition and conversion time=4+12+2=18 clock cycles for 1 sample

For 1 Million samples per second we need 18 Million SAR Clock cycles.

1. End of Scan: This interrupt occurs when the ADC has completed scanning all enabled channels. It is useful for applications requiring multi-channel data acquisition, ensuring all channels are read before processing the data.
2. Overflow: This interrupt triggers when the result register is updated before the previous result is read. It helps detect and handle situations where the ADC is running faster than the system can read results, preventing data loss.
3. Collision: This occurs when a new trigger is received while the ADC is still processing the previous trigger. It helps manage situations where multiple triggers could interfere with each other, ensuring proper timing and data integrity.
4. Injection EOC (End of Conversion): This interrupt happens when the injection channel conversion is complete. It is useful in systems with priority channels, allowing immediate processing of critical signals without waiting for other channels.
5. Range Detection: This interrupt is triggered when the channel result meets a predefined threshold value. It is beneficial for applications needing real-time monitoring of signals, such as detecting out-of-range conditions and taking immediate action.
6. Saturation Detection: This occurs when the channel result is equal to the minimum or maximum value of the set resolution. It is useful for identifying when the input signal is too high or too low, preventing erroneous data from affecting the system’s performance.

The registers that should/can be used to control and use ADC are given above and are self explanatory.

This is the LDR module given to us by infineon to run a application that reads values from the LDR and stores in a variable which we can see using the debug functionality of VS Code.

GPIO Configuration for ADC Pin: The ADC input pin is configured in the user_cfg.c file:

const cy_stc_gpio_pin_config_t ADC_P2_0_config = 
{
 .outVal = 1,
 .driveMode = 0x09UL,
 .intEdge = 0x00UL,
 .vtrip = 0,
 .slewRate = 0,
};

ADC Channel Configuration: The ADC channel configuration is defined in user_cfg.c:

const cy_stc_sar_channel_config_t pass_0_sar_0_channel_0_config = 
{
    .addr = (cy_en_sar_chan_config_port_pin_addr_t)(CY_SAR_ADDR_SARMUX_0),
    .differential = false,
    .resolution = 0UL,
    .avgEn = false,
    .sampleTimeSel = 0UL,
    .rangeIntrEn = false,
    .satIntrEn = false,
};

This structure configures channel 0 for single-ended input with a specified address and other settings.

ADC Configuration: The main ADC configuration is defined in user_cfg.c:

const cy_stc_sar_config_t pass_0_sar_0_config = 
{
    .vrefSel = 7UL, //CY_SAR_VREF_SEL_VDDA - 5V
    .vrefBypCapEn = false,
    .negSel = 0UL, //CY_SAR_NEG_SEL_VSSA_KELVIN - Negative ip selection
    .negVref = 1UL,
    .boostPump = false,
    .power = 1UL,
    .sarMuxDsEn = false,
    .switchDisable = false,
    .subResolution = 1UL, //10-bit Sub resolution
    .leftAlign = false,
    .singleEndedSigned = true,
    .differentialSigned = true,
    .avgCnt = 7UL,
    .avgShift = true,
    .trigMode = 0UL,
    .eosEn = false,
    .sampleTime0 = 13,
    .sampleTime1 = 2,
    .sampleTime2 = 2,
    .sampleTime3 = 2,
    .rangeThresLow = 0UL,
    .rangeThresHigh = 0UL,
    .rangeCond = 0UL,
    .chanEn = 1UL,
    .channelConfig = {&pass_0_sar_0_channel_0_config, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
    .routingConfig = NULL,
    .vrefMvValue = 5000UL,
};

• This structure sets the reference voltage, power, resolution, alignment, and other parameters for the ADC.

Initialization and Enabling: In the main() function of main.c, the ADC is initialized and enabled:

Cy_SAR_Init(SAR0, &pass_0_sar_0_config);
init_cycfg_peripherals();
Cy_SAR_Enable(SAR0);

ADC Usage

1. Starting Conversion: In the main loop of main.c, an ADC conversion is started:

Cy_SAR_StartConvert(SAR0, 1u);//ADC.c

2. Reading the Result: After starting the conversion, the result is read and stored:

chanresult = Cy_SAR_GetResult16(SAR0, 0u);//ADC.c

All in all it was a fantastic class full of learnings. If you liked this article please do give a clap!